As the integration density (e.g. the number of features per square unit area) of semiconductor devices continues to increase, methods of increasing the pattern resolution during exposure of a semiconductor substrate using a photolithographic mask are desirable. Resolution may be determined based on the well-known Rayleigh's equation. Light sources having shorter wavelengths have been investigated to increase resolution. For example, photolithography processes have progressed from using emissions at the G-line at 436 nm of an Hg source, to the I-line at 365 nm of an Hg source, followed by a KrF laser of 248 nm, then an ArF laser of 193 nm, and presently an F2 laser of 157 nm as the light source. In addition, processes using X-rays and/or electron beams as the light sources are under development. Development of short-wavelength light sources and corresponding photoresist materials, while costly, has helped increase the integration density of semiconductor devices.
A method of forming a fine pattern is disclosed in U.S. Pat. No. 5,686,223 entitled “Method for Reduced Pitch Lithography” to Cleeves. According to Cleeves, first and second photoresist patterns are formed by performing a photo process twice. In particular, after a first photoresist pattern is formed on a substrate by a first photo process and then stabilized, a second photoresist pattern is formed on the substrate having the first photoresist pattern. However, when the second photoresist pattern is formed by the second photo process, it may be misaligned. In particular, a problem may occur when photoresist patterns are required to be spaced apart from each other by a uniform distance.
In order to make a discrete device perform its own function without interfering with adjacent devices, it is desirable to utilize an isolation technique to electrically and structurally isolate the discrete devices. To increase integration density, it is desirable to reduce not only the dimensions of the discrete devices, but also the area and width of isolation regions between devices. The isolation technique may affect integration density, and may be important to the reliable electrical performance of the device. The trench isolation technique is widely used in semiconductor device fabrication, and has the advantage of avoiding the “bird's beak” problem that may occur when a conventional local oxidation of silicon (LOCOS) process is used for isolation. The trench isolation technique includes forming a hard mask pattern that exposes a field region and covers an active region on a semiconductor substrate, etching the substrate within the field region using the hard mask pattern as an etch mask to form a trench, and filling the trench with an insulating material to form an isolation structure between devices. However, as integration density increases, it may be desirable to reduce the pitch of the hard mask pattern. The pitch of the photoresist pattern may be reduced in order to form a hard mask pattern having a reduced pitch. Accordingly, it may be desirable to use photolithography equipment having a short wavelength light source, along with a corresponding photoresist material. However, the development of new photolithography equipment to replace that used in conventional processes may be costly and/or time-consuming.